The present invention relates generally to semiconductor device manufacturing and, more particularly, to contact resistivity reduction in transistor devices by deep level impurity formation.
Integrated circuits (ICs) include a multitude of transistors formed on a semiconductor substrate. Transistors such as, for example, metal oxide semiconductor field effect transistors (MOSFETs) are generally built on the top surface of a bulk substrate. The substrate is doped to form impurity-diffusing layers (i.e., source and drain regions). Located between the source and drain regions is a conductive layer, separated by a thin dielectric layer, which operates as a gate for the transistor. The gate controls current in a channel formed between the source and the drain regions.
In order to reduce series resistance associated with the source and drain regions of a MOSFET, semiconductor manufacturers employ a self-aligned silicide or “salicide” process also known as silicidation. Typically, silicidation is accomplished by depositing a refractory metal (e.g., cobalt (Co), titanium (Ti), nickel (Ni), platinum (Pt), tungsten (W), etc.) onto an exposed surface of source and drain regions in a semiconductor substrate. During an annealing process, the atoms of silicon (Si) in the source and drain regions react with the atoms of the refractory metal, thereby forming a silicide layer. Those portions of the refractory metal on insulating regions remain unreacted and can be selectively removed. The remaining layer of silicide reduces the contact resistance at the silicide source/drain junction by helping break through the residual surface oxide so that good electrical contact can be made.
Silicon MOSFET scaling requires the continuous reduction of the gate length, gate dielectric thickness, and higher substrate doping. As these parameters improve, the intrinsic device resistance scales below 1000Ω-μm, leading to faster devices. However, as such devices scale down in size, the silicide material used to contact the source and drain regions becomes an increasingly limiting factor on device speed with respect to the parasitic contact resistance of silicide-to-silicon in the source/drain (S/D) contacts. This is because minimizing the silicide interface resistivity depends mainly on maximizing the S/D doping level, which is already at saturation levels in current CMOS technology.
Accordingly, as devices scale smaller, the contact resistance only increases as the silicide/silicon contact area becomes smaller. Thus, not only in relative terms, but also in absolute terms, the contact resistance increases as devices scale below 0.1 μm, which in turn places a severe limitation on potential device improvement obtained by scaling other parameters.